a. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to forming source/drain regions in 3D CMOS structures.
b. Background of Invention
Providing stress within the source/drain (S/D) regions of, for example, planar CMOS transistors, may account for about a 25 to 35 percent enhancement in device performance that is attributable to increased channel mobility. Generally, in 2-dimensional (2D) transistor structures, embedded silicon-germanium (SiGe) or silicon-carbon (Si:C) S/D regions may exert compressive or tensile stress on the channel region of the device.
However, 3-dimensional devices such as FinFet transistors may typically include raised S/D regions and may not, therefore, have embedded (S/D) regions capable of exerting sufficient longitudinal stress within the channel region of the Fin in comparison to 2D planar structures.